module memoryManager (
    input wire clk,
    input wire rst,
    input wire ram_pick,
    input wire write_en,
    input wire [9:0] write_size,
    input wire [5:0] write_priority,
    input wire [5:0] write_port,
    input wire data_en_in,
    input wire [31:0] data_in,
    input wire queue_update_en,
    input wire [7:0] is_first_tail,
    input wire [9:0] queue_tail_old,
    input wire [15:0] queue_tail_new,
    input wire dequeue_en,
    input wire [7:0] is_last_head,
    input wire [9:0] dequeue_head_old,
    input wire [15:0] enqueue_sucess,
    output wire enqueue_en_out,
    output wire [5:0] enqueue_priority_out,
    output wire [9:0] enqueue_value_out,
    output wire [5:0] enqueue_port_out,
    output reg dequeue_head_new_en,
    output reg [5:0] dequeue_head_new_port,
    output reg [5:0] dequeue_head_new_priority,
    output reg [15:0] dequeue_head_new_value,
    output wire address_ready,
    output wire manager_write_ready,
    output wire [31:0] data_out
);
    //RAM驱动信号
    wire write_padding_out;                 
    wire write_en_out;  
    wire [14:0] write_address_out;
    wire [31:0] write_data_out;
    wire read_en_out;
    wire [14:0] read_address_out;
    wire [9:0] read_size_out;
    //RAM控制信号
    wire ena;
    wire wea;
    wire [14:0] addra;
    wire [31:0] dina;
    wire enb;
    wire web;
    wire [14:0] addrb;
    wire [31:0] dinb;
    wire [31:0] data_out_a;


    //空间分配
    memoryAlloctor alloctor(.clk(clk), .rst(rst), 
                            .ram_pick(ram_pick), .write_en(write_en), .write_size(write_size), .write_priority(write_priority), .write_port(write_port), 
                            .data_en_in(data_en_in), .data_in(data_in), 
                            .queue_update_en(queue_update_en), .is_first_tail(is_first_tail), .queue_tail_old(queue_tail_old), .queue_tail_new(queue_tail_new), 
                            .dequeue_en(dequeue_en), .is_last_head(is_last_head), .dequeue_head_old(dequeue_head_old), .enqueue_sucess(enqueue_sucess),
                            .enqueue_en(enqueue_en_out), .enqueue_port(enqueue_port_out), .enqueue_priority(enqueue_priority_out), .enqueue_value(enqueue_value_out), 
                            .dequeue_head_new_en(dequeue_head_new_en), .dequeue_head_new_port(dequeue_head_new_port), .dequeue_head_new_priority(dequeue_head_new_priority), .dequeue_head_new_value(dequeue_head_new_value), 
                            .address_ready(address_ready), .manager_write_ready(manager_write_ready),
                            .write_padding_out(write_padding_out), .write_en_out(write_en_out), .write_address_out(write_address_out), .write_data_out(write_data_out), 
                            .read_en_out(read_en_out), .read_address_out(read_address_out), .read_size_out(read_size_out));
    

    //RAM读写驱动器
    memoryWorker worker(.clk(clk), .rst(rst), .wr_padding_en(write_padding_out), .wr_en(write_en_out), .wr_address(write_address_out), .wr_data(write_data_out), .rd_en(read_en_out), .rd_address(read_address_out), .ena(ena), .wea(wea), .addra(addra), .dina(dina), .enb(enb), .web(web), .addrb(addrb), .dinb(dinb));

    //RAM
    RAM ram(.clka(clk), .ena(ena), .wea(wea), .addra(addra), .dina(dina), .douta(), .clkb(clk), .enb(enb), .web(web), .addrb(addrb), .dinb(dinb), .doutb(data_out));
endmodule